Printed circuit boards for high speed logic.    

fig52- Multilayer Printed Circuit Board

High speed (1 nsec.) logic systems require voltage planes to separate successive layers of signal lines (Fig.52) in order to keep signal cross coupling (noise) down to a reasonable level (say 10% of signal amplitude).At a frequency of 1 GHz, skin depth in copper is  cm. (=0.00008 in.) (Ref.20). At 10 GHz, skin depth drops to  cm. (=0.00003 in.).The thinnest practicable laminated copper is about 0.001 in., which is more than ten times the skin depth. This means that in practice, a signal travelling down a signal line and returning by the immediately adjacent voltage plane(s) will not penetrate beyond the plane(s), and each voltage plane will screen signals above it from signals below it with negligible crosstalk through voltage plane. So long as a signal is transmitted down between a signal line and the voltage plane(s) immediately above and/or below it, the only crosstalk (noise) of significance will be between (adjacent) signal lines in the same plane[1]. Care must be taken that at its source and destination, the signal is referenced to the correct voltage plane(s), and this will now be discussed.

Calculation.

As a practical example, consider (Fig.49) a surface passive line with potentially active lines on each side of it, with w=0.010" and d=0.010".

FX from one adjacent line is 11%, so from the two active lines it is 22%. This is rather high unless the lines are short. We might therefore reduce h by  from 0.008" to 0.006". The effect is about  the same as increasing d by  to 0.013", which reduces FX to an acceptable 8%, or 16% for the two active lines[2].

DX is given in one curve only in Figure 49, and this curve relates to w=0.010". With w=0.010" and d=0.010" the velocity difference F is 15%, or 0.15.  It can be shown that as a % of the active signal,

 

where F is the % velocity difference,

Assume; the length of the passive line ;  the velocity of propagation  per nsec in an epoxy-glass PCB; and the active signal rise time  For w=0.010" and d=0.010, Figure 49 shows that F=15%, or 0.15 .  Thus,  

Decoupling by Voltage Planes.

Fig24 - Parallel plates

In order to understand the nature of the decoupling action at a point between parallel voltage planes, first consider the parallel-plate transmission line (Fig.24), which has a . This formula still applies for each small section of a transmission line where the width a is varying, for example for a wedge-shaped line (Fig.53.).

fig53- Voltage plane decoupling

Over a distance  the above formula becomes

.

Now if , we are considering a complete plane. The signal travels out radially between the planes (Ref.21), and we get

.

Now we know that, in a medium of permittivity e and permeability m, the outwards velocity of the signal through the epoxy-glass dielectric is

.

Therefore

,

where t is the time since the signal was introduced at the centre.
So using this last equation for the distance r we get

 

where a is in metres.

A reflection related to  arrives back at the centre at time 2t. If  is small when , (the risetime of the output of the logic gate,) then natural decoupling between planes is satisfactory.

Calculation.

As a practical example, if 2t=1ns, d=0.5mm., , then

 

This calculation shows that natural decoupling between voltage planes is satisfactory for a single switching load of high speed logic, or for a number of loads in the same integrated circuit[3]. We then prevent superposition of the current transients into a number of integrated circuits switching at the same instant from  generating unacceptably large voltage transients between planes by adding extra discrete (  ) decoupling capacitors distributed at intervals of a few centimetres. The proportion of the surface area occupied by the miniature tantalum capacitors will be insignificant.



[1]
One argument which can be used to dismiss the feared additional effect of a further active line next to the nearest active line is as follows. In Figure 49, if line width w and line spacing d are both 0.010", then maximum FX is 11%. However, the next parallel active line is at a spacing d of 0.030", causing it to add a negligible further FX of 2.5%. The reality, of course, is that the nearer active line shields the further active line from the passive line.

[2]
There is, however, a price to be paid for reducing h by 3/4 to 0.006" (equivalent to w=0.013", h=0.008"), because, see Figure 47, Zo drops from 74 ohms to 64 ohms. As a result, it takes more current to drive the line, slowing down driving circuit and increasing power dissipation. Generally, reducing crosstalk by hiding lines close to planes (a) reduces (impedance and therefore) speed and (b) increases power dissipation.

[3]
perhaps switching a transient 100ma or 500mw. Think of a 5v power supply with source impedance of 0.2 ohms driving a 50 ohm load, resulting in a drop of (0.2/50.2)..5v=20mv across the source and a drop of the effective supply from 5v to 4.98v.